1. Field of the Invention
The present invention relates to strained semiconductor devices that incorporate strained active layers and methods for making such devices. The invention more specifically relates to methods of making strained semiconductor devices in which biaxial strain can be provided to the active regions of small geometry devices.
2. Description of the Related Art
Strained silicon is widely viewed as an important technology for obtaining desired advancements in integrated circuit performance. Mobility enhancement results from a combination of reduced effective carrier mass and reduced intervalley (phonon) scattering. For MOS field effect transistors (MOSFETs) fabricated on conventional {100} oriented silicon substrates with conduction primarily along <110> crystal axes, n-channel MOSFETs achieve improved performance with induced biaxial tensile strain in the top silicon layer along both the width and length axes of the active area. p-channel MOSFETs exhibit improved performance with induced uniaxial tensile strain in the top silicon layer along the width axis only (transverse tensile strain), p-channel MOSFETs also exhibit improved performance with induced uniaxial compressive strain in the top silicon layer along the length axis only (longitudinal compressive strain). Compressive strain can be provided selectively in a silicon surface layer, for example, by using recessed selective epitaxial silicon germanium stressors in the source and drain regions of a MOSFET to induce a desired uniaxial compressive strain along the length axis (longitudinal).
Strained silicon is conventionally obtained by first growing a thick layer of silicon germanium alloy (SiGe) on a silicon substrate. The silicon germanium layer is caused to be relaxed to an unstrained condition at its surface either by deliberately growing the layer to a thickness exceeding its critical thickness or otherwise inducing misfit dislocations, for example by implantation of ions. The in-plane lattice parameter of the silicon germanium surface is similar to that of a bulk crystal of silicon germanium of the same composition. Silicon germanium alloys have larger lattice parameters than silicon. Hence the relaxed surface of the silicon germanium layer provides an in-plane lattice parameter larger than that of silicon. A subsequent thin layer of silicon is grown epitaxially on the relaxed surface of the silicon germanium layer. The thin epitaxial layer of silicon assumes the larger in-plane lattice parameter of the silicon germanium and grows in a strained state with bonds in the crystal lattice elongated in the growth plane. This approach, sometimes known as substrate-strained silicon or “virtual substrate” technology, grows a thin pseudomorphic layer of silicon on the relaxed surface of a silicon germanium layer.
So long as the strained silicon layer does not exceed a “critical thickness” for strain relaxation and some care is taken, the tensile strain is maintained in the strained silicon layer throughout the various implantation and thermal processing steps typical of CMOS manufacturing.
The use of a relaxed silicon germanium layer as a “virtual substrate” to strain a subsequently deposited epitaxial silicon layer inevitably requires acceptance of a very high dislocation density in the silicon germanium layer because the silicon germanium relaxation mechanism is plastic in nature. In other words, relaxation in the silicon germanium layer occurs through the generation of strain-relieving misfit dislocations. A silicon germanium layer thinner than the critical thickness on a silicon substrate is not relaxed and exhibits few misfit dislocations. If the silicon germanium layer is thicker than the critical thickness, the strained lattice undergoes plastic deformation and the stress is relieved to some degree by the nucleation and propagation of misfit dislocations. Some fraction of misfit dislocations gives rise to threading dislocations (at least 104-105 cm−2) which propagate through the overlying strained silicon layer. Threading dislocations represent extended defects and give rise to multiple undesirable consequences in MOSFETs including source/drain junction leakage, reduction of channel mobility, variability of threshold voltage and enhanced diffusion paths leading to potential drain-to-source shorting in short-channel MOSFETs.
Contemporary FET and contact manufacturing strategies are illustrated in Jan, et al., “A 45 nm Low Power System-On-Chip Technology with Dual Gate (Logic and I/O) High-k/Metal Gate Strained Silicon Transistors,” International Electron Devices Meeting (IEDM) 2008, and in Watanabe, et al., “A Low Power 40 nm CMOS Technology Featuring Extremely High Density of Logic (2100 kGate/mm2) and SRAM (0.195 μm2) for Wide Range of Mobile Applications with Wireless System,” International Electron Devices Meeting (IEDM) 2008. These papers each describe high-density, low-power devices that can be used in system-on-chip applications such as are commonly used in wireless systems.